As the desire to integrate more and more transistors onto a single substrate continues to grow, new technologies are developed. Previously, increases in transistor density were largely achieved by the miniaturization of the transistor itself. However, as geometries have continued to shrink, the widths of certain features, such as transistor gates may be less than ten atomic layers. Thus, there is a physical limit to the degree of miniaturization that is possible.
In an attempt to continuing integrating more transistors on a single device, the concept of vertical devices, also known as 3D devices, has gained momentum. Briefly, traditional transistors are made with the source, drain and gate region horizontally oriented. Vertical gates stack these features in the vertical direction, thereby reducing the horizontal footprint of each device. Various techniques are being proposed by various semiconductor manufacturers.
However, there are challenges associated with vertical devices. Specifically, with respect to certain vertical non-volatile memory (NVM) devices, such as NAND FLASH devices, the concept of string current has been discussed as a potential issue. The string current, or current in the vertical direction in a NVM memory device, is a function of the doping concentration of a polycrystalline channel. Inadequate or non-uniform doping of this channel may degrade the device operating parameters and performance. In addition, non-uniform doping of this channel may affect the threshold voltage of the different cells along that channel. These issues may impact certain types of NVM memory devices, including NAND FLASH devices. Similar challenges requiring controlled doping of vertical layers also occur in other types of NVM memory devices, such as resistive memory cells, which include but are not limited to ReRAM, PCRAM, and CBRAM devices. Additionally, other type of devices may have similar challenges.
Therefore, it would be beneficial if there were a method of doping a sidewall in a high aspect ratio feature, such as the trenches and vias in a vertical NVM device, such that performance parameters were optimized.